2

Analysis of the subthreshold CMOS logic inverter

Year:
2016
Language:
english
File:
PDF, 2.23 MB
english, 2016
3

Time-Domain Readout of 1T–1C DRAM Cells

Year:
2018
Language:
english
File:
PDF, 937 KB
english, 2018
7

Reading DRAM cells using two properly designed cascaded inverters

Year:
2014
Language:
english
File:
PDF, 1.17 MB
english, 2014
15

Performance optimization of 1T-1C DRAMs: A quantitative study

Year:
2016
Language:
english
File:
PDF, 4.32 MB
english, 2016
17

A novel high-performance time-balanced wide fan-in CMOS circuit

Year:
2016
Language:
english
File:
PDF, 1.93 MB
english, 2016
24

A novel high-speed CMOS circuit based on a gang of capacitors

Year:
2017
Language:
english
File:
PDF, 846 KB
english, 2017
25

Understanding the behavior of RTD-loaded NMOS inverter through compact-form analysis

Year:
2017
Language:
english
File:
PDF, 2.07 MB
english, 2017
26

A voltage-controlled ring oscillator based on an FGMOS transistor

Year:
2017
Language:
english
File:
PDF, 2.19 MB
english, 2017
27

A Novel Low-Latency DRAM Based on the Bitline-Discharge Rate

Year:
2018
Language:
english
File:
PDF, 1.19 MB
english, 2018
28

A predischarged bitline 1T-1C DRAM readout scheme

Year:
2019
Language:
english
File:
PDF, 2.23 MB
english, 2019